1. Field of the Invention
The present invention relates to a method for manufacturing a lightly-doped drain (LDD) type metal oxide semiconductor (MOS) device.
2. Description of the Related Art
In a fine-structured MOS device, in order to avoid deterioration of characteristics due to hot carriers, an LDD type structure has been used.
In a first prior art method for manufacturing an LDD type MOS transistor (see FIGS. 2A to 2G of JP-A-1-189964 and FIG. 2 of JP-A-4-346476), a gate electrode is formed via a gate insulating layer on a P-type semiconductor substrate. Then, N-type impurity ions such as phosphorous ions are implanted into the semiconductor substrate with a mask of the gate electrode, to form a lean, i.e., low concentration N-type impurity region in the semiconductor substrate. Then, a sidewall insulating layer is formed on a sidewall of the gate electrode, and N-type impurity ions such as arsenic ions are implanted into the semiconductor substrate with a mask of the gate electrode and the sidewall insulating layer to form a rich, i.e., high concentration N.sup.+ -type impurity region in the semiconductor substrate. This will be explained later in detail.
Thus, in the first prior art manufacturing method, the N.sup.- -type impurity region and the N.sup.+ -type impurity region are in self-alignment with the gate electrode. However, a channel region beneath the gate electrode into which P-type impurity ions such as boron ions are implanted to adjust the threshold voltage is not in self-alignment with the gate electrode, since such ion implantation is carried out before the formation of the gate electrode. Therefore, the transistor characteristics such as the threshold voltage and the breakdown voltage fluctuate in accordance with the fluctuation of location of the channel region. Also, the size of the gate electrode is determined by a lithography process using an exposure system, and therefore, it is impossible to reduce the size of the gate electrode smaller than a minimum size determined by the exposure system. For example, a gate length of sub .mu. smaller than 0.5 .mu.m cannot be obtained.
In a second prior art method for manufacturing an LDD type MOS transistor (see JP-A-63-67778), a gate electrode is formed via a gate insulating layer on a P-type semiconductor substrate. Then, N-type impurity ions such as arsenic ions are implanted into the semiconductor substrate with a mask of the gate electrode, to form a rich, i.e., high concentration N.sup.+ -type impurity region in the semiconductor substrate. Then, the gate electrode is etched by an isotropical etching process, to form a reduced gate electrode. Then, a sidewall insulating layer is formed on a sidewall of the reduced gate electrode, and N-type impurity ions such as phosphorous ions are implanted into the semiconductor substrate with a mask of the reduced gate electrode and the sidewall insulating layer to form a lean, i.e., low concentration N.sup.- -type impurity region in the semiconductor substrate. This will be explained later in detail.
Thus, also in the second prior art manufacturing method, the N.sup.- -type impurity region and the N.sup.+ -type impurity region are in self-alignment with the gate electrode. Also, in this case, however, a channel region beneath the gate electrode into which P-type impurity ions such as boron ions are implanted to adjust the threshold voltage is not in self-alignment with the gate electrode, since such ion implantation is carried out before the formation of the gate electrode. Therefore, the transistor characteristics such as the threshold voltage and the breakdown voltage fluctuate in accordance with the fluctuation of location of the channel region. Since an isotropical etching process is used, the reduced gate electrode, which is smaller than a minimum size determined by an exposure system can be obtained. For example, a gate length of sub .mu. smaller than 0.5 .mu.m can be obtained. However, the size of such a reduced gate electrode is variable.
In a third prior art method for manufacturing an LDD type MOS transistor (see FIG. 1 of JP-A-4-346476), a silicon oxide layer is formed on a P-type semiconductor silicon substrate, and an opening is perforated in the silicon oxide layer. Then sidewall insulating layer is formed on a sidewall of the silicon oxide layer by an anisotropical reactive ion etching (RIE) process. In this case, the semiconductor substrate is also etched by the RIE process. Then, the semiconductor substrate is thermally oxidized to form a gate silicon oxide layer therein. Then, a gate electrode is formed on the gate silicon oxide layer and the sidewall insulating layer. Then, N-type impurity ions such as arsenic ions are implanted into the semiconductor substrate with a mask of the gate electrode and the sidewall insulating layer to form a rich, i.e., high concentration N.sup.+ -type impurity region. Then, the sidewall, insulating layer is removed. Then, N-type impurity ions such as phosphorous ions are implanted into the semiconductor substrate with a mask of the gate electrode to form a lean, i.e., low concentration N.sup.- -type impurity region. This will be explained later in detail.
Thus, also in the third prior art manufacturing method, the N.sup.- -type impurity region and the N.sup.+ -type impurity region are in self-alignment with the gate electrode. Also, in this case, a channel region beneath the gate electrode into which P-type impurity ions such as boron ions are implanted to adjust the threshold voltage is in self-alignment with the gate electrode. Further, a reduced gate electrode, which is smaller than a minimum size determined by an exposure system can be obtained. For example, a gate length of sub .mu. smaller than 0.5 .mu.m can be obtained. However, since the gate electrode is partly buried in the semiconductor substrate, the semiconductor substrate is so damaged that defects are easily created in the channel region. As a result, the performance and reliability of the MOS transistor is deteriorated.